Spacer scheme for semiconductor device
US9269811B2 · kind B2 · utility
3Cited by
90References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.