Processor and instruction processing method in processor
US9274794B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Oct 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.