Programmable test chip, system and method for characterization of integrated circuit fabrication processes
US9275187B2 · kind B2 · utility
1Cited by
16References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG16H40/67
- WIPO fieldMedical technology
- WIPO sectorInstruments
Abstract
A test chip, system and method for testing large numbers of test devices on a single test chip decreases the time and complexity required to characterize the variation and reliability of the IC fabrication process. A remotely configurable test chip can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes. An on-chip addressing technique allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test chip may be configured for wafer, die or package-level testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.