Memory banks with shared input/output circuitry
US9275686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | May 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.