Energy conservation in a multicore chip
US9275696B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory (DRAM) that stores a cache coherence directory of a multicore chip. More particularly, a directory entry may be accessed in the cache coherence directory stored in the DRAM. Some further examples may identify a cache coherence state of a block associated with the directory entry. In some examples, refresh of the directory entry stored in the DRAM may be selectively disabled based on the identified cache coherence state of the block such that energy associated with the multicore chip is conserved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.