Three dimensional cross-access dual-port bit cell design
US9275710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory comprises a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for read and write of one or more bits of data to the cross-access dual port bit cell. The semiconductor memory further comprises a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on one or more cross-access dual-port bit cells in the row. The semiconductor memory further comprises a pair of column selection lines associated with at least one of the plurality of columns of the dual port memory array, wherein the pair of column selection lines is configured to carry a pair of column selection signals for enabling the cross-access dual-port bit cells in the column during the read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.