Method and apparatus for high yield contact integration scheme
US9275889B2 · kind B2 · utility
3Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Oct 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.