Process for fabricating an integrated circuit having trench isolations with different depths
US9275891B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | May 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.