Inventor · Grenoble, FR

Claire Fenouillet-Beranger

37Patents

5h-index

29Co-inventors

65Inventor score

Filing activity: Jun 16, 2006 → Jul 21, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7687872B2	Back-lit image sensor with a uniform substrate temperature	Electricity	181	Active
US7910419B2	SOI transistor with self-aligned ground plane and gate and buried oxide of variable thickness	Electricity	107	Active
US7804134B2	MOSFET on SOI device	Electricity	14	Active
US9502566B2	Method for producing a field effect transistor including forming a gate after forming the source and drain	Electricity	9	Active
US7556995B2	MOS transistor manufacturing	Electricity	7	Active
US9666577B2	On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges	Electricity	3	Active
US9165943B2	ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges	Electricity	3	Active
US9337302B2	On-SOI integrated circuit comprising a subjacent protection transistor	Electricity	2	Active
US9793162B2	Method for producing interconnections for 3D integrated circuit	Electricity	2	Active
US10115637B2	Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit	Electricity	2	Active
US9761583B2	Manufacturing of self aligned interconnection elements for 3D integrated circuits	Electricity	2	Active
US8383464B2	Method for producing field effect transistors with a back gate and semiconductor device	Electricity	1	Active
US8314453B2	SRAM memory cell with four transistors provided with a counter-electrode	Electricity	1	Active
US9391057B2	Integrated circuit on SOI comprising a transistor protecting from electrostatic discharges	Electricity	1	Active
US11631609B2	Method for manufacturing a microelectronic device	Electricity	0	Active
US8048751B2	Method for producing a field effect device having self-aligned electrical connections with respect to the gate electrode	Electricity	0	Active
US9275891B2	Process for fabricating an integrated circuit having trench isolations with different depths	Electricity	0	Active
US10062681B2	SOI integrated circuit equipped with a device for protecting against electrostatic discharges	Electricity	0	Active
US9852950B2	Superimposed transistors with auto-aligned active zone of the upper transistor	Electricity	0	Active
US9653476B2	On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges	Electricity	0	Active
US7749858B2	Process for producing an MOS transistor and corresponding integrated circuit	Electricity	0	Active
US8936993B2	Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate	Electricity	0	Active
US8674443B2	Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrate	Electricity	0	Active
US10074802B2	Device with transistors distributed over several superimposed levels integrating a resistive memory	Electricity	0	Active
US9786658B2	Fabrication method of a stack of electronic devices	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.