Methods of fabricating semiconductor devices having buried channel array
US9276074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Oct 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.