High performance interconnect physical layer
US9280507B2 · kind B2 · utility
2Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2013 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jan 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.