Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
US9281043B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Dec 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.