Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information
US9281048B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Jul 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.