Semiconductor structure
US9281195B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Apr 2, 2013 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Apr 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.