Non-volatile memory with a single gate-source common terminal and operation method thereof
US9281312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.