Super junction semiconductor device and associated fabrication method
US9281393B2 · kind B2 · utility
8Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Mar 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A semiconductor device with a substrate, an epitaxy layer formed on the substrate, a plurality of deep wells formed in the epitaxy layer, a plurality of trench gate MOSFET units each of which is formed in top of the epitaxy layer between two adjacent deep well, wherein a trench gate of the trench gate MOSFET unit is shallower than half of the distance between two adjacent deep wells, which may reduce the product of on-state resistance and the gate charge of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.