Intra-instructional transaction abort handling
US9286076B2 · kind B2 · utility
25Cited by
16References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/467
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.