Processor scheduling with thread performance estimation on cores of different types
US9286128B2 · kind B2 · utility
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Nov 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described having an out-of-order core to execute a first thread and a non-out-of-order core to execute a second thread. The processor also includes statistics collection circuitry to support calculation of the following: the first thread's performance on the out-of-order core; an estimate of the first thread's performance on the non-out-of-order core; the second thread's performance on the non-out-of-order core; an estimate of the second thread's performance on the out-of-order core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.