Fault-aware mapping for shared last level cache (LLC)
US9286172B2 · kind B2 · utility
3Cited by
4References
24Claims
0Family size
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Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.