Apparatus for capturing results of memory testing
US9286181B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Oct 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.