Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array
US9286955B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6878
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.