Method of fabricating FinFETs
US9287129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.