Adhesive pattern for advance package reliability improvement
US9287233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Jan 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.