Dummy flip chip bumps for reducing stress
US9287234B2 · kind B2 · utility
8Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Sep 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.