Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

US9287362B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anirban Basu · Elmsford, US
• Cheng-Wei Cheng · White Plains, US
• Wilfried E. Haensch · Somers, US
• Amlan Majumdar · White Plains, US
• Kuen-Ting Shiu · Yorktown Heights, US

Key dates

• Filing date: Nov 21, 2014
• Grant date: Mar 15, 2016
• Expiry date: Nov 21, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8162

Abstract

An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.