Method of manufacturing a gate trench with thick bottom oxide
US9287376B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Dec 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated gate trench is manufactured by forming a first dielectric layer on a semiconductor substrate, forming a hardmask on the first dielectric layer and etching a trench into the semiconductor substrate through an opening in the hardmask and the first dielectric layer, the trench having sidewalls and a bottom. The sidewalls and bottom of the trench are lined with a second dielectric layer without an intervening oxide layer along the sidewalls and bottom of the trench. The second dielectric layer is removed from at least part of the bottom of the trench to expose part of the semiconductor substrate, and the exposed part of the semiconductor substrate is removed to form an oxide region at the bottom of the trench. Subsequently, a gate dielectric is formed on the sidewalls and bottom of the trench and a gate electrode in the trench without a separate field electrode in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.