Dual-mode transistor devices and methods for operating same
US9287406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.