Integrated circuit with low power scan flip-flop
US9291674B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.