Selective raid protection for cache memory
US9292228B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Feb 6, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jun 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.