Instruction set architecture with opcode lookup using memory attribute
US9292290B2 · kind B2 · utility
13Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Jul 23, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.