Pulsed-latch based razor with 1-cycle error recovery scheme
US9292390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.