Design-Based weighting for logic built-in self-test
US9292399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.