Data cache prefetch controller
US9292447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.