Cache memory data compression and decompression

US9292449B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Alaa R. Alameldeen · Madison, US
• Niranjan L. Cooray · Folsom, US
• Jayesh Gaur · Bengaluru, IN
• Steven D. Pudar · Sunnyvale, US
• Manuel A. Aguilar Arreola · Folsom, US
• Margareth E. Marrugo · Cameron Park, US
• Chinnakrishnan Ballapuram · San Jose, US

Key dates

• Filing date: Dec 20, 2013
• Grant date: Mar 22, 2016
• Expiry date: Apr 24, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/401
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.