Methods and apparatus for intra-set wear-leveling for memories with limited write endurance
US9292451B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Oct 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.