Layout optimization for integrated circuit design
US9292645B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jan 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.