Patent · US Active

System for partitioning integrated circuit design based on timing slack

US9292651B2 · kind B2 · utility

0Cited by

6References

6Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Chetan Verma · Sunnyvale, US
Amit Kumar Dey · Noida, IN
Ashis Maitra · Bengaluru, IN
Kulbhushan Misri · Barwala, IN
Amit Roy · Noida, IN
Harkaran Singh · Noida, IN
Vijay Tayal · Noida, IN

Key dates

Filing date	Mar 3, 2014
Grant date	Mar 22, 2016
Priority date	—
Expiry date	Jul 2, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.