Dot inversion configuration
US9293076B2 · kind B2 · utility
0Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides systems, methods and apparatus for an arrangement of pixels and interconnects in a display. In one aspect, polarities of pixels may be in a dot inversion configuration, or checkerboard pattern, to reduce the visibility of flicker. Various interconnect alternatively couple between modules in different columns or rows to provide dot inversion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.