Three terminal fuse with FinFET
US9293221B1 · kind B1 · utility
1Cited by
14References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2015 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.