Semiconductor package with improved redistribution layer design and fabricating method thereof
US9293403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.