Method for interconnecting die and substrate in an electronic package
US9293440B2 · kind B2 · utility
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5References
8Claims
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Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for interconnecting a die on a substrate of an electronic package. The method includes the steps of forming a plurality of free-end wire bonds on the die, wherein the free-end wire bonds are upstanding from the die, and encapsulating the free-end wire bonds in an encapsulation layer. Planarizing the encapsulation layer is performed so that the free-end wire bonds are exposed for electrical connection. Interconnecting the free-end wire bonds is provided by applying an interconnection layer on the encapsulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.