Wafer level packaging bond
US9293445B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jan 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.