Power MOSFET current sense structure and method

US9293535B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Peilin Wang · Beijing, CN
• Jingjing Chen · Fuzhou, CN
• Edouard D. de Frésart · Tempe, US
• Pon Sung Ku · Gilbert, US
• Wenyi Li · Shanghai, CN
• Ganming Qin · Chandler, US

Key dates

• Filing date: Sep 12, 2012
• Grant date: Mar 22, 2016
• Expiry date: Sep 12, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.