Patent · US Active

Semiconductor structure including a ferroelectric transistor and method for the formation thereof

US9293556B2 · kind B2 · utility

9Cited by

0References

11Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Ralf van Bentum · Radebeul, DE
Jongsin Yun · Austin, US
Seunghwan Seo · Dresden, DE
Joerg Schmid · Dresden, DE

Key dates

Filing date	Jul 29, 2014
Grant date	Mar 22, 2016
Priority date	—
Expiry date	Aug 1, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0177
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.