High voltage III-nitride semiconductor devices
US9293561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Apr 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.