Semiconductor memory device and method of manufacturing the same
US9293563B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jun 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.