Variable resistance memory device and a method of fabricating the same
US9293701B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Oct 29, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Oct 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.