Hybrid synchronous/asynchronous counter
US9294099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.