Capacitance multiplier and loop filter noise reduction in a PLL
US9294106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.