Methods and systems of synchronizer selection
US9294263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | May 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W56/001
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.